Subthreshold SRAM Design for Energy Efficient Applications in Nanometric CMOS Technologies

Embedded SRAM circuits are vital components in a modern system on chip (SOC) that can occupy up to 90% of the total area. Therefore, SRAM circuits heavily affect SOC performance, reliability, and yield. In addition, most of the SRAM bitcells are in standby mode and significantly contribute to the total leakage current and leakage power consumption. The aggressive demand in portable devices and billions of connected sensor networks requires long battery life. Therefore, careful design of SRAM circuits with minimal power consumption is in high demand. Reducing the power consumption is mainly achieved by reducing the power supply voltage in the idle mode. However, simply reducing the supply voltage imposes practical limitations on SRAM circuits such as reduced static noise margin, poor write margin, reduced number of cells per bitline, and reduced bitline sensing margin that might cause read/write failures. In addition, the SRAM bitcell has contradictory requirements for read stability and writability. Improving the read stability can cause difficulties in a write operation or vice versa. In this thesis, various techniques for designing subthreshold energy-efficient SRAM circuits are proposed. The proposed techniques include improvement in read margin and write margin, speed improvement, energy consumption reduction, new bitcell architecture and utilizing programmable wordline boosting. A programmable wordline boosting technique is exploited on a conventional 6T SRAM bitcell to improve the operational speed. In addition, wordline boosting can reduce the supply voltage while maintaining the operational frequency. The reduction of the supply voltage allows the memory macro to operate with reduced power consumption. To verify the design, a 16-kb SRAM was fabricated using the TSMC 65 nm CMOS technology. Measurement results show that the maximum operational frequency increases up to 33.3% when wordline boosting is applied. Besides, the supply voltage can be reduced while maintaining the same frequency. This allows reducing the energy consumption to be reduced by 22.2%. The minimum energy consumption achieved is 0.536 fJ/b at 400 mV. Moreover, to improve the read margin, a 6T bitcell SRAM with a PMOS access transistor is proposed. Utilizing a PMOS access transistor results in lower zero level degradation, and hence higher read stability. In addition, the access transistor connected to the internal node holding V DD acts as a stabilizer and counterbalances the effect of zero level degradation. In order to improve the writability, wordline boosting is exploited. Wordline boosting also helps to compensate for the lower speed of the PMOS access transistor compared to a NMOS transistor. To verify our design, a 2kb SRAM is fabricated in the TSMC 65 nm CMOS technology. Measurement results show that the maximum operating frequency of the test chip is at 3.34 MHz at 290 mV. The minimum energy consumption is measured as 1.1 fJ/b at 400 mV

Antioxidant activity of different parts of Tetrataenium lasiopetalum.

In Iranian traditional medicine, different species of the genus Tetrataenium are used as antiseptic, spice and food additives.The present study examined the possible antioxidant effects of hydro-alcoholic extracts of different parts of Tetrataenium lasiopetalum (Boiss.) Manden (Apiaceae).Laminas, stems, petioles, fruits, peduncles and flowers of T. lasiopetalum were collected, dried and then extracted by ethanol and water (70:30). Antioxidant activities of extracts were examined by employing different in vitro assays, i.e., 1,1-diphenyl-2-picrylhydrazyl (DPPH) radical scavenging, metal chelating, reducing power activities and hemoglobin-induced linoleic acid system. Also, total phenolic and flavonoid contents of the extracts were evaluated.Hydro-alcoholic extract of T. lasiopetalum flower showed the highest activity in scavenging of DPPH (IC50 = 170 ± 7 μg/mL). In metal chelating assay, lamina extract possesses a better iron ion chelating activity than other extracts (230 ± 10 μg/mL). Lamina hydro-alcoholic extract demonstrated better activity in reducing the power and hemoglobin-induced linoleic acid system than other parts of T. lasiopetalum.These results showed the antioxidant activity of different parts of T. lasiopetalum based on its usage in traditional medicine

A Real-Time Thermal Monitoring System Intended for Embedded Sensors Interfaces

RÉSUMÉ: This paper proposes a real-time thermal monitoring method using embedded integrated sensor interfaces dedicated to industrial integrated system applications. Industrial sensor interfaces are complex systems that involve analog and mixed signals, where several parameters can influence their performance. These include the presence of heat sources near sensitive integrated circuits, and various heat transfer phenomena need to be considered. This creates a need for real-time thermal monitoring and management. Indeed, the control of transient temperature gradients or temperature differential variations as well as the prediction of possible induced thermal shocks and stress at early design phases of advanced integrated circuits and systems are essential. This paper addresses the growing requirements of microelectronics applications in several areas that experience fast variations in high-power density and thermal gradient differences caused by the implementation of different systems on the same chip, such as the new-generation 5G circuits. To mitigate adverse thermal effects, a real-time prediction algorithm is proposed and validated using the MCUXpresso tool applied to a Freescale embedded sensor board to monitor and predict its temperature profile in real time by programming the embedded sensor into the FRDM-KL26Z board. Based on discrete temperature measurements, the embedded system is used to predict, in advance, overheating situations in the embedded integrated circuit (IC). These results confirm the peak detection capability of the proposed algorithm that satisfactorily predicts thermal peaks in the FRDM-KL26Z board as modeled with a finite element thermal analysis tool (the Numerical Integrated elements for System Analysis (NISA) tool), to gauge the level of local thermomechanical stresses that may be induced. In this paper, the FPGA implementation and comparison measurements are also presented. This work provides a solution to the thermal stresses and local system overheating that have been a major concern for integrated sensor interface designers when designing integrated circuits in various high-performance technologies or harsh environment

A gain-of-function mutation of STAT1: A novel genetic factor contributing to chronic mucocutaneous candidiasis

Heterozygous gain-of-function (GOF) mutations in the signal transducer and activator of transcription 1 (STAT1) have increasingly been identified as a genetic cause of autosomal-dominant (AD) chronic mucocutaneous candidiasis (CMC). In this article, we describe a 33-year-old man who experienced chronic refractory candidiasis, recurrent otitis media, and pneumonia resulting in bronchiectasis, severe oral and esophageal candidiases with strictures associated with hypothyroidism and immune hemolytic anemia. His son also suffered from persistent candidiasis, chronic diarrhea, poor weight gain, and pneumonia that resulted in his demise because of sepsis. The immunological workup showed that an inverse CD4/CD8 ratio and serum immunoglobulins were all within normal ranges. The laboratory data revealed failure in response to Candida lymphocyte transformation test. In addition, by Sanger sequencing method, we found a heterozygous mutation, Thr385Met (T385M), located in the DNA-binding domain of STAT1, which was previously shown to be GOF. These findings illustrate the broad and variable clinical phenotype of heterozygous STAT1 GOF mutations. However, more clinical information and phenotype–genotype studies are required to define the clinical phenotype caused by AD STAT1 GOF

Low fingertip temperature rebound measured by digital thermal monitoring strongly correlates with the presence and extent of coronary artery disease diagnosed by 64-slice multi-detector computed tomography

Previous studies showed strong correlations between low fingertip temperature rebound measured by digital thermal monitoring (DTM) during a 5 min arm-cuff induced reactive hyperemia and both the Framingham Risk Score (FRS), and coronary artery calcification (CAC) in asymptomatic populations. This study evaluates the correlation between DTM and coronary artery disease (CAD) measured by CT angiography (CTA) in symptomatic patients. It also investigates the correlation between CTA and a new index of neurovascular reactivity measured by DTM. 129 patients, age 63 ± 9 years, 68% male, underwent DTM, CAC and CTA. Adjusted DTM indices in the occluded arm were calculated: temperature rebound: aTR and area under the temperature curve aTMP-AUC. DTM neurovascular reactivity (NVR) index was measured based on increased fingertip temperature in the non-occluded arm. Obstructive CAD was defined as ≥50% luminal stenosis, and normal as no stenosis and CAC = 0. Baseline fingertip temperature was not different across the groups. However, all DTM indices of vascular and neurovascular reactivity significantly decreased from normal to non-obstructive to obstructive CAD [(aTR 1.77 ± 1.18 to 1.24 ± 1.14 to 0.94 ± 0.92) (P = 0.009), (aTMP-AUC: 355.6 ± 242.4 to 277.4 ± 182.4 to 184.4 ± 171.2) (P = 0.001), (NVR: 161.5 ± 147.4 to 77.6 ± 88.2 to 48.8 ± 63.8) (P = 0.015)]. After adjusting for risk factors, the odds ratio for obstructive CAD compared to normal in the lowest versus two upper tertiles of FRS, aTR, aTMP-AUC, and NVR were 2.41 (1.02–5.93), P = 0.05, 8.67 (2.6–9.4), P = 0.001, 11.62 (5.1–28.7), P = 0.001, and 3.58 (1.09–11.69), P = 0.01, respectively. DTM indices and FRS combined resulted in a ROC curve area of 0.88 for the prediction of obstructive CAD. In patients suspected of CAD, low fingertip temperature rebound measured by DTM significantly predicted CTA-diagnosed obstructive disease

A gate sizing and transistor fingering strategy for subthreshold CMOS circuits

Parallel Transistor Stacks (PTS) has been shown to be an effective technique for improving the speed of digital circuits operating in the subthreshold region which comes at the cost of power consumption and area. However, our experience shows that using PTS is not beneficial in all cases. In this paper, we present a methodology to identify whether using PTS is beneficial (or not) in a particular CMOS technology and what transistor sizing can be employed to maximize the circuit speed. Our technique is based on analyzing the Current-Over- Capacitance (COC) ratio of PMOS and NMOS transistors. The results of incorporating the proposed methodology in a 4-bit comparator and a 19-stage inverter ring oscillator, using 90 nm CMOS technology, illustrate 26% and 40% extra improvement compared to the blind use of PTS, respectively